1. Field of the Invention
The invention relates to a phase locked loop (PLL) circuit, and more particularly to a dual-loop PLL circuit for locking a signal with a low frequency.
2. Description of the Related Art
In conventional dual-loop phase locked loop (PLL) circuits, if an input clock signal with a low frequency, such as 15K˜100K Hz for video applications, is input to the dual-loop PLL circuit to serve as a reference clock and an output clock signal with a low frequency, such as 10M˜300M Hz, is generated by the main PLL loop of the dual-loop PLL circuit, a low pass filter in the main PLL loop is required to have a large capacitor to degrade output jitter. However, the low pass filter with a large capacitor in the main PLL loop occupies a large area, and the whole area of the dual-loop PLL circuit is thus increased.
Thus, it is desired to provide a dual-loop PLL circuit with a small low pass filter for locking a low frequency.